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Allwinner /D1H /SMHC[2] /SMHC_THLD

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Interpret as SMHC_THLD

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (disabled)CARD_RD_THLD_ENB 0 (disabled)BCIG 0 (disabled)CARD_WR_THLD_ENB 0CARD_WR_THLD

CARD_WR_THLD_ENB=disabled, BCIG=disabled, CARD_RD_THLD_ENB=disabled

Description

Card Threshold Control Register

Fields

CARD_RD_THLD_ENB

Card Read Threshold Enable

0 (disabled): Card read threshold disabled

1 (enabled): Card read threshold enabled
BCIG

Busy Clear Interrupt Generation

0 (disabled): Busy clear interrupt disabled

1 (enabled): Busy clear interrupt enabled
CARD_WR_THLD_ENB

Card Read/Write Threshold Enable

0 (disabled): Card write threshold disabled

1 (enabled): Card write threshold enabled
CARD_WR_THLD

Card Read/Write Threshold Size

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data